AVX512_VNNI is not enabled on Cascade Lake-SP

General Discussion
1

I thought Intel Deep Learning Boost AVX512_VNNI was suppose to be a supported cpu instruction on Cascade Lake-SP 2nd Gen Xeon, however, it’s not operational at all? Fix?

root@r940xa~ # uname -a
Linux r940xa 6.12.1-1499.native #1 SMP PREEMPT Wed Nov 27 10:18:00 PST 2024 x86_64 GNU/Linux
root@r940xa~ # cpuid | grep AVX512_VNNI | head -1
      AVX512_VNNI: neural network instructions = false
root@r940xa~ # lscpu
Architecture:             x86_64
  CPU op-mode(s):         32-bit, 64-bit
  Address sizes:          46 bits physical, 48 bits virtual
  Byte Order:             Little Endian
CPU(s):                   224
  On-line CPU(s) list:    0-223
Vendor ID:                GenuineIntel
  BIOS Vendor ID:         Intel
  Model name:             Intel(R) Xeon(R) Platinum 8280L CPU @ 2.60GHz
    BIOS Model name:      Intel(R) Xeon(R) Platinum 8280L CPU @ 2.60GHz  CPU @ 2.6GHz
    BIOS CPU family:      179
    CPU family:           6
    Model:                85
    Thread(s) per core:   2
    Core(s) per socket:   28
    Socket(s):            4
    Stepping:             5
    CPU(s) scaling MHz:   99%
    CPU max MHz:          3900.0000
    CPU min MHz:          1000.0000
    BogoMIPS:             5200.00
    Flags:                fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb
                           rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl
                           vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lah
                          f_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3 intel_ppin ssbd mba ibrs ibpb stibp tpr_shadow flexpriority ept vpid ept_ad fsgsbase
                          tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd avx51
                          2bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local dtherm ida arat pln pts vnmi pku ospke md_cl
                          ear flush_l1d arch_capabilities
Virtualization features:
  Virtualization:         VT-x
Caches (sum of all):
  L1d:                    3.5 MiB (112 instances)
  L1i:                    3.5 MiB (112 instances)
  L2:                     112 MiB (112 instances)
  L3:                     154 MiB (4 instances)
NUMA:
  NUMA node(s):           1
  NUMA node0 CPU(s):      0-223
Vulnerabilities:
  Gather data sampling:   Vulnerable: No microcode
  Itlb multihit:          KVM: Vulnerable
  L1tf:                   Not affected
  Mds:                    Vulnerable; SMT vulnerable
  Meltdown:               Not affected
  Mmio stale data:        Vulnerable
  Reg file data sampling: Not affected
  Retbleed:               Vulnerable
  Spec rstack overflow:   Not affected
  Spec store bypass:      Vulnerable
  Spectre v1:             Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers
  Spectre v2:             Vulnerable; IBPB: disabled; STIBP: disabled; PBRSB-eIBRS: Not affected; BHI: Not affected
  Srbds:                  Not affected
  Tsx async abort:        Vulnerable
2

I don’t have either on hand just at the moment to double check cpuid output but VNNI is an Ice Lake feature.

3

The Intel web page does indeed list the 8280L CPU as having support for Deep Learning Boost. Intel® Xeon® Platinum 8280L Processor
There’s also a nice discussion of the differences in implementations between Cascade Lake and Ice Lake generations at Solved: How to confirm whether my CPU support VNNI or not? - Intel Community and Which AVX-512 Instructions are Supported by Intel® Xeon®… also corroborates with this.

Chris

4

it seems the tool you use only lists the kernel features (from /proc/cpuinfo) but nowadays the kernel policy is to only list the features the kernel uses there … not every single bit of ISA the cpu supports